Processor architectures
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Intel processors
Current architectures: SandBridge and its sucessors (IvyBridge) Next architectures: Haswell (by March 2013)
New manycore architecture: Intel MIC (Many Integrated Core) Products: Knights Ferry , Knights Corner (Xeon Phi, 2012), Knights Landing
Intel uses Tick-Tock principle for the developing cycle of their processors. "Tick-Tock" is a model adopted Intel since 2007 to follow every microarchitectural change with a die shrink of the process technology. Every "tick" is a shrinking of process technology of the previous microarchitecture and every "tock" is a new microarchitecture. Every year, there is expected to be one tick or tock.
SandyBridge architecture
Sandy Bridge is a microprocessor architecture developed by Intel for central processing units in computers to replace the Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.
Sandy Bridge processors are originally produced in 32nm technology, while subsequent products, Ivy Bridge processors, use 22nm technology. Main advantages include:
- 32KB data + 32KB instruction L1 cache and 256KB L2 cache per core
- Shared L3 cache includes the processor graphics
- 64-byte CPU cache line size
- Two load/store operations per CPU cycle for each memory channel
- Decoded micro-operation cache and enlarged, optimized branch predictor
- Improved performance for criptography
- 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain
- Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality
- Intel Quick Sync Video, hardware support for video encoding and decoding
- Up to 8 physical cores or 16 logical cores through Hyper-threading
Haswell architecture
Haswell is a microprocessor architecture developed as the successor to the Ivy Bridge architecture. Haswell will be the first processor to be designed from the ground up to fully optimize the power savings and performance benefits from the move to 3D or tri-gate transistors on the 22nm process node. Haswell will also increase the perfromance of integrated GPU bringing it closely to those of $50 - $70 graphics cards.
Main improvements include:
- Haswell New Instructions (includes Advanced Vector Extensions 2 (AVX2), gather, bit manipulation, and FMA3 support)
- New sockets — LGA 1150 for desktops and rPGA947 & BGA1364 for the mobile market
- Intel Transactional Synchronization Extensions (TSX)
- Three versions of the integrated GPU
- Graphics support in hardware for Direct3D 11.1 and OpenGL 4.0
- DDR4 for the enterprise/server variant (Haswell-EX)
- Variable Base clock like LGA 2011
- A new cache design
- 128-byte CPU cache line size
- New advanced power-saving system
- Up to 32MB Unified cache LLC (Last Level Cache)
Future architectures
Broadwell will be the 14nm shrink of the Haswell architecture. Broadwell will adopt the Multi-Chip Package (MCP) design, so that could mean that Haswell motherboards might not be compatible with Broadwell motherboards.
Skylake is the codename for a processor microarchitecture to be developed by Intel as the successor to the Haswell architecture. Skylake will use a 14 nm process. Skymont will be the 10 nm shrink of Skylake and is due out the year after the introduction of the Skylake microarchitecture.
Many Integrated Cores (MIC)
Intel Many Integrated Core Architecture or Intel MIC is a multiprocessor computer architecture developed by Intel. The Intel Many Integrated Core architecture brings an SMP programming environment onto a single chip. A co-processor, code-named Knights Corner will be the first Intel product using the Intel MIC architecture. A prototype, called Knights Ferry, was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with 4 threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache),and a power requirement of ~300 W,built at a 45 nm process.
AMD processors
Current architectures: Bulldozer, Fusion Next architectures: Bulldozer improvements - Piledriver (2012), Steamroller (2013), Excavator (2014)
Buldozer architecture
Bulldozer is Advanced Micro Devices' (AMD) Accelerated Processing Unit (APU) codename for the server and desktop processors released in October 2011.
Main improvements include:
- "Clustered Integer Core" micro-architecture
- 2MB of L2 per CPU module
- Support for Intel's Advanced Vector Extensions (AVX) instruction set
- New instrcution set (XOP, FMA4 and CVT16) proposed by AMD
- 32 nm production process
- Native DDR3 memory support up to DDR3-1866[17]
- Dual Channel DDR3 integrated memory controller for Desktop and Server/Workstation processors
- Quad Channel DDR3 Integrated Memory Controller for Server/Workstation processors
Fusion architecture
AMD Fusion is the name for a series of Accelerated Processing Unit by AMD, aimed at providing good performance with low power consumption, and integrating a CPU and a GPU based on a mobile stand-alone GPU. The final design is the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of modern GPUs (like GPGPU computation) into a single die. This technology was shown to the general public in 2011. Second-generation is expected in 2012.
The 2011 platform integrates CPU, GPU, Northbridge, PCIe, DDR3 memory controller, and UVD on the same integrated circuit. The CPU and GPU are coupled together using a memory controller that arbitrates between coherent and non-coherent memory request. The physical memory is partitioned: up to 512 MB + virtual for GPU, remainder + virtual for the CPU. The 2012 platform will allow the GPU to access the CPU memory without going through a device driver. The 2013 platform will use a unified memory controller for both CPU and GPU. The 2014 platform will add hardware context switching for the GPU.[5]
AMD is set to launch a "fully integrated" APU in 2014. According to AMD, the APU will feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement
NVIDIA Graphics Processing Units
NVIDIA gave preview of its new generation of GPU arhictecture in GTC 2012 conference, San Jose, California. The new GPU architecture is called Kepler. There are two different Kepler GPUs in development. The Kepler1 (GK104) chip, also known as , is aimed at graphics cards and Tesla GPU coprocessors, where single-precision floating point math is what matters most. Kepler2 (GK110) GPUs will be tuned for double-precision floating point math and will support more GDDR5 memory with ECC support. Kepler2 will have different packaging aimed at servers, and will cost more money than Tesla cards based on the Kepler1 units. Nvidia increased the core counts and slowed down the clock speeds, increasing the parallelism and the overall performance of GPU while significantly lowering its power draw and heat dissipation.
New features:
- New SMX (Streaming Multiprocessor eXtreme) architecture with 192 CUDA cores per multiprocesor
- The core speed is 1006MHz, with turbo boost option allowing 1058MHz
- About three times better performance per watt of power consumption
- New Hyper-Q technology that enables multiple MPI tasks to run in parallel on the GPU (up to 32 MPI tasks)
- Dynamic parallelism - GPU can adapt to data and one kernel can dynamically launch another kernel.
